1. Field of the Invention
Generally, the present disclosure generally relates to the manufacturing of sophisticated semiconductor devices, and, more specifically, to various methods of forming metal silicide regions on semiconductor devices.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein field effect transistors (NMOS and PMOS transistors) represent one important type of circuit element used in manufacturing such integrated circuit devices. A field effect transistor, irrespective of whether an NMOS transistor or a PMOS transistor is considered, typically comprises doped source and drain regions that are formed in a semiconducting substrate that are separated by a channel region. A gate insulation layer is positioned above the channel region and a conductive gate electrode is positioned above the gate insulation layer. By applying an appropriate voltage to the gate electrode, the channel region becomes conductive and current is allowed to flow from the source region to the drain region.
For many early device technology generations, the gate electrode structures of most transistor elements has comprised a plurality of silicon-based materials, such as a silicon dioxide and/or silicon oxynitride gate insulation layer, in combination with a polysilicon gate electrode. However, as the channel length of aggressively scaled transistor elements has become increasingly smaller, many newer generation devices employ gate electrode stacks comprising alternative materials in an effort to avoid the short-channel effects which may be associated with the use of traditional silicon-based materials in reduced channel length transistors. For example, in some aggressively scaled transistor elements, which may have channel lengths of on the order of approximately 14-32 nm, gate electrode stacks comprising a so-called high-k dielectric/metal gate (HK/MG) configuration have been shown to provide significantly enhanced operational characteristics over the heretofore more commonly used silicon dioxide/polysilicon (SiO/poly) configurations. These metal gate electrode materials may include, for example, one or more layers of titanium (Ti), titanium nitride (TiN), titanium-aluminum (TiAl), aluminum (Al), aluminum nitride (AlN), tantalum (Ta), tantalum nitride (TaN), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), tantalum silicide (TaSi), and the like.
One well-known processing method that has been used for forming a transistor with a high-k/metal gate structure is the so-called “gate last” or “replacement gate” technique. FIGS. 1A-1D depict one illustrative prior art method for forming an HK/MG replacement gate structure using a gate-last technique. As shown in FIG. 1A, the process includes the formation of a basic transistor structure 100 above a semiconducting substrate 10 in an active area defined by a shallow trench isolation structure 11. At the point of fabrication depicted in FIG. 1A, the device 100 includes a sacrificial gate insulation layer 12, a dummy or sacrificial gate electrode 14, sidewall spacers 16, a layer of insulating material 17 and source/drain regions 18 formed in the substrate 10. The various components and structures of the device 100 may be formed using a variety of different materials and by performing a variety of known techniques. For example, the sacrificial gate insulation layer 12 may be comprised of silicon dioxide, the sacrificial gate electrode 14 may be comprised of polysilicon, the sidewall spacers 16 may be comprised of silicon nitride and the layer of insulating material 17 may be comprised of silicon dioxide. The source/drain regions 18 may be comprised of implanted dopant materials (N-type dopants for NMOS devices and P-type dopant for PMOS devices) that are implanted into the substrate 10 using known masking and ion implantation techniques. Of course, those skilled in the art will recognize that there are other features of the transistor 100 that are not depicted in the drawings for purposes of clarity. For example, so called halo implant regions are not depicted in the drawings as well as various layers or regions of silicon germanium that are typically found in high-performance PMOS transistors. At the point of fabrication depicted in FIG. 1A, the various structures of the device 100 have been formed and a chemical mechanical polishing process (CMP) has been performed to remove any materials above the sacrificial gate electrode 14 (such as a protective cap layer (not shown) comprised of silicon nitride) so that the sacrificial gate electrode 14 may be removed.
As shown in FIG. 1B, one or more etching processes are performed to remove the sacrificial gate electrode 14 and the sacrificial gate insulation layer 12 to thereby define a gate opening 20 where a replacement gate structure will subsequently be formed. A masking layer that is typically used in such etching processes is not depicted for purposes of clarity. Typically, the sacrificial gate insulation layer 12 is removed as part of the replacement gate technique, as depicted herein. However, the sacrificial gate insulation layer 12 may not be removed in all applications.
Next, as shown in FIG. 1C, various layers of material that will constitute a replacement gate structure 30 are formed in the gate opening 20. In one illustrative example, the replacement gate structure 30 is comprised of a high-k gate insulation layer 30A having a thickness of approximately 2 nm, a work-function adjusting layer 30B comprised of a metal (e.g., a layer of titanium nitride with a thickness of 2-5 nm) and a bulk metal layer 30C (e.g., aluminum). Ultimately, as shown in FIG. 1D, a CMP process is performed to remove excess portions of the gate insulation layer 30A, the work-function adjusting layer 30B and the bulk metal layer 30C positioned outside of the gate opening 20 to define the replacement gate structure 30.
In a field effect transistor, metal silicide regions are typically formed in the source/drain regions of a transistor to reduce the resistance when a conductive contact is formed to establish electrical connection to the source/drain regions. The typical steps performed to form metal silicide regions are: (1) depositing a layer of refractory metal; (2) performing an initial heating process causing the refractory metal to react with underlying silicon containing material; (3) performing an etching process to remove unreacted portions of the layer of refractory metal and (4) performing an additional heating process to form the final phase of the metal silicide. The details of such silicidation processes are well known to those skilled in the art.
The present disclosure is directed to various, more efficient methods of forming metal silicide regions on semiconductor devices.